//;******************************************************************************
//;* Project: MCU OS for Cap touch using Sitronix A8008 IC.
//;* Author: Benson Shen (Jun. 20, 2013)
//;* Copyright (C) 2013, Sitronix Tech. Corp.
//;******************************************************************************

#ifndef	__CTI2C_C_FUNCTABLE_DEF_H__
#define	__CTI2C_C_FUNCTABLE_DEF_H__

//==[I2C Protocol Ver]==
#define		REG_ST_PROTOCOL_VER				0x25
#define		REG_FT_PROTOCOL_VER				0x08
#define		REG_GT_PROTOCOL_VER				0x01//GT960


////Host interface registers
////====[Read Cmd]====
#define 	REG_FIRMWARE_VERSION			0x00
#define 	REG_STATUS						0x01
//	#define 	REG_STATUS_DEVICE				(BIT3|BIT2|BIT1|BIT0)
//		#define		REG_STATUS_DEVICE_NORMAL				0x0
//		#define		REG_STATUS_DEVICE_INIT					0x1
//		#define		REG_STATUS_DEVICE_ERROR					0x2
//		#define		REG_STATUS_DEVICE_AUTO_TUNING			0x3
//		#define		REG_STATUS_DEVICE_IDLE					0x4
//		#define		REG_STATUS_DEVICE_PWR_DN				0x5
//		#define		REG_STATUS_DEVICE_BOOT_ROM				0x6	
//		#define		REG_STATUS_DEVICE_ICRC					0x7	
//	
//	#define 	REG_STATUS_ERROR				(BIT7|BIT6|BIT5|BIT4)
//		#define 	REG_STATUS_ERROR_NO_ERROR				0x0
//		#define 	REG_STATUS_ERROR_INVALID_ADDR			0x1
//		#define 	REG_STATUS_ERROR_INVALID_VALUE			0x2
//		#define 	REG_STATUS_ERROR_INVALID_PLATFORM		0x3
//		#define 	REG_STATUS_ERROR_DEV_NOT_FOUND			0x4
//		#define 	REG_STATUS_ERROR_STACK_OVERFLOW			0x5		
//		#define 	REG_STATUS_ERROR_CONFIG_TABLE_VER		0x6// ConfigTableVer and ConfigTableChkSum is Err
//		#define 	REG_STATUS_ERROR_ALGO_ROM_TAG_ERR		0x7
	
////====[Write Cmd]====
#define 	REG_DEVICE_CTRL					0x02
	#define		REG_DEVICE_CTRL_DEFAULT			0x00
	#define 	REG_DEVICE_CTRL_RESET			BIT0
	#define 	REG_DEVICE_CTRL_POWER_DOWN		BIT1
	#define 	REG_DEVICE_CTRL_PROXI_EN		BIT2
	#define 	REG_DEVICE_CTRL_GEST_EN			BIT3
	#define 	REG_DEVICE_CTRL_ALGO_DATA		(BIT3|BIT2)
		#define		REG_DEVICE_CTRL_ALGO_DATA_1D_0			0<<2
		#define		REG_DEVICE_CTRL_ALGO_DATA_1D_1			1<<2
		#define		REG_DEVICE_CTRL_ALGO_DATA_2D			2<<2
		#define		REG_DEVICE_CTRL_ALGO_DATA_RESERVED		3<<2	
	#define 	REG_DEVICE_CTRL_FLASH_UPD_DIS	BIT6
	#define 	REG_DEVICE_CTRL_AUTOTUNE		BIT7
#define 	REG_TIMEOUT_TO_IDLE				0x03
	#define		REG_TIMEOUT_TO_IDLE_VALUE		0x2//0x02//0x02	//idle 8 Sec//00->Idle Mode

#define 	REG_XY_RESOLUTION_H				0x04
	#define 	X_RESOLUTION_H					0x01	//480
	#define 	Y_RESOLUTION_H					0x02	//640	
#define 	REG_X_RESOLUTION_L				0x05
	#define 	X_RESOLUTION_L					0xE0	//480
#define 	REG_Y_RESOLUTION_L				0x06
	#define 	Y_RESOLUTION_L					0x80	//640

#define 	REG_SENSING_COUNTER_H			0x07
#define 	REG_SENSING_COUNTER_L			0x08

#define 	REG_I2C_CMD_0x09				0x09
#define 	REG_RAW_DATA_CRC				0x0A
#define		REG_FW_TYPE						0x0B
////====[Read Cmd]====
#define 	REG_FIRMWARE_REVERSION_3		0x0C
#define 	REG_FIRMWARE_REVERSION_2		0x0D
#define 	REG_FIRMWARE_REVERSION_1		0x0E
#define 	REG_FIRMWARE_REVERSION_0		0x0F
#define 	REG_FINGERS_GESTURE				0x10
#define 	REG_KEYS_REG					0x11
#define 	REG_XY0_COORD_H					0x12
#define 	REG_X0_COORD_L					0x13
#define 	REG_Y0_COORD_L					0x14
#define 	REG_Z0_COORD					0x15
#define 	REG_XY1_COORD_H					0x16
#define 	REG_X1_COORD_L					0x17
#define 	REG_Y1_COORD_L					0x18
#define 	REG_Z1_COORD					0x19
#define 	REG_XY2_COORD_H					0x1A
#define 	REG_X2_COORD_L					0x1B
#define 	REG_Y2_COORD_L					0x1C
#define 	REG_Z2_COORD					0x1D
#define 	REG_XY3_COORD_H					0x1E
#define 	REG_X3_COORD_L					0x1F
#define 	REG_Y3_COORD_L					0x20
#define 	REG_Z3_COORD					0x21
#define 	REG_XY4_COORD_H					0x22
#define 	REG_X4_COORD_L					0x23
#define 	REG_Y4_COORD_L					0x24
#define 	REG_Z4_COORD					0x25
#define 	REG_XY5_COORD_H					0x26
#define 	REG_X5_COORD_L					0x27
#define 	REG_Y5_COORD_L					0x28
#define 	REG_Z5_COORD					0x29

#define		REG_CONTACT_COUNT_MAX			0x3F


//====[Data Out Packet]====
#define		REG_DATA_OUTPUT_PACKET			0x40
#define		REG_DATA_OUT_TYPE				REG_DATA_OUTPUT_PACKET
	#define		REG_DATA_OUT_NOT_READY			0x00
	#define		REG_DATA_OUT_ALGO_1D_0			0x01
	#define		REG_DATA_OUT_ALGO_1D_1			0x02
	#define		REG_DATA_OUT_ALGO_2D			0x03
	#define		REG_DATA_OUT_RAW_1D_0			0x04
	#define		REG_DATA_OUT_RAW_1D_1			0x05
	#define		REG_DATA_OUT_RAW_2D				0x06
	#define		REG_DATA_OUT_RAW_KEY			0x07
	#define		REG_DATA_OUT_ALGO2_1D_0			0x84
	#define		REG_DATA_OUT_ALGO2_1D_1			0x85
	#define		REG_DATA_OUT_ALGO2_2D			0x86
	#define		REG_DATA_OUT_ALGO2_KEY			0x87		

#define		REG_DATA_OUT_VALID_SIZE			0x41
#define		REG_DATA_OUT_START_CH_H			0x42
#define		REG_DATA_OUT_START_CH_L			0x43
#define		REG_DATA_OUT_VALID_RAW			0x44


//====[Command IO Port]====
#define		REG_CMD_IO_CMD_ID				0xD0
	#define		CMD_IO_H2D_CMD_WR_RAM_ROM		0x01
		#define		CMD_IO_H2D_WRTC_MEMORY			0x00
		#define		CMD_IO_H2D_WRTC_SFRS			0x01
	#define		CMD_IO_H2D_CMD_RD_RAM_ROM		0x02
		#define		CMD_IO_H2D_RDTC_MEMORY			0x00
		#define		CMD_IO_H2D_RDTC_SFRS			0x01
		#define		CMD_IO_H2D_RDTC_ROM				0x02
	#define		CMD_IO_H2D_CMD_SPECIFY_SENSING	0x03
	#define		CMD_IO_H2D_CMD_GET_INF			0x04

	#define		CMD_IO_D2H_CMD_ERR_MESSAG		0x81
	#define		CMD_IO_D2H_CMD_RD_RAM_ROM		0x82
	#define		CMD_IO_D2H_CMD_DEV_OUT_INF		0x84
		#define		DEV_OUT_INF_INFO_ID				1
		#define		DEV_OUT_INF_INFO_VER			1
		#define		DEV_OUT_INF_RAW_DATA_REF_VALUE	0		
		#define		DEV_OUT_INF_RAW_DATA_FORMAT1	1
		#define		DEV_OUT_INF_RAW_DATA_FORMAT2	2

#define		REG_CMD_IO_VALID_SIZE			0xD1
#define		REG_CMD_IO_TYPE					0xD2
#define		REG_CMD_IO_SPECIFY_NUMOFBLK		0xD2
#define		REG_CMD_IO_ADDR_H				0xD3
#define		REG_CMD_IO_SPECIFY_BLK0			0xD3
#define		REG_CMD_IO_ADDR_L				0xD4
#define		REG_CMD_IO_SIZE					0xD5
#define		REG_CMD_IO_DATA0				0xD6


#define		REG_MISC_INF					0xF0
	#define		REG_MISC_INF_1D_XY				0
	#define		REG_MISC_INF_1D_X				1
	#define		REG_MISC_INF_1D_Y				2
	#define		REG_MISC_INF_1D_NO				3
#define		REG_MISC_CTRL					0xF1
#define		REG_SMART_WAKEUP_ID				0xF2

#define		REG_CHIP_ID						0xF4
#define		REG_NUM_X						0xF5
#define		REG_NUM_Y						0xF6
#define		REG_NUM_KEY_PROX				0xF7
#define 	REG_H2D_CMD_PACKET_READY		0xF8
	#define		CMD_IO_PASS						0x00
	#define		CMD_IO_UNKNOW_CMD_ID			0x80
	#define		CMD_IO_H2D_CMD_CHKSUM_ERR		0x81
#define		REG_GET_RAW_DATA_PACKET_FINISH	0xF9

#define		REG_MESSAGE_PORT_CMD			0xFC
	#define		REG_MESSAGE_PORT_CMD_DIS		0x00
	#define		REG_MESSAGE_PORT_CMD_EN			0x01
	#define		REG_MEG_PORT_GET_GPIO_STS		0x80
#define		REG_SUB_PAGE_CMD				0xFE
#define		REG_PAGE_CMD					0xFF
	#define		REG_PAGE_CMD_REPORT_ID			0x00
	#define		REG_PAGE_CMD_DEVE_ID			0xEF




#define	REG_EX_I2C_ADDR			0x100
//REG_EX_FIRMWARE_VERSION		    EQU	EDATA 	REG_EX_I2C_ADDR+REG_FIRMWARE_VERSION//0x00	
//REG_EX_STATUS					EQU	EDATA 	REG_EX_I2C_ADDR+REG_STATUS//0x01						
//REG_EX_DEVICE_CTRL				EQU	EDATA 	REG_EX_I2C_ADDR+REG_DEVICE_CTRL//0x02					   
//REG_EX_TIMEOUT_TO_IDLE			EQU	EDATA 	REG_EX_I2C_ADDR+REG_TIMEOUT_TO_IDLE//0x03				  
//REG_EX_XY_RESOLUTION_H			EQU	EDATA 	REG_EX_I2C_ADDR+REG_XY_RESOLUTION_H//0x04			 
//REG_EX_X_RESOLUTION_L			EQU	EDATA 	REG_EX_I2C_ADDR+REG_X_RESOLUTION_L//0x05				  
//REG_EX_Y_RESOLUTION_L			EQU	EDATA 	REG_EX_I2C_ADDR+REG_Y_RESOLUTION_L//0x06			 
//REG_EX_SENSING_COUNTER_H		EQU	EDATA 	REG_EX_I2C_ADDR+REG_SENSING_COUNTER_H//0x07			  
//REG_EX_SENSING_COUNTER_L		EQU	EDATA 	REG_EX_I2C_ADDR+REG_SENSING_COUNTER_L//0x08			 
//REG_EX_I2C_0x09					EQU	EDATA 	(REG_EX_I2C_ADDR+0x09)//0x09				    
//REG_EX_RAW_DATA_CRC				EQU	EDATA 	REG_EX_I2C_ADDR+REG_RAW_DATA_CRC//0x0A	
//REG_EX_FW_TYPE					EQU	EDATA 	REG_EX_I2C_ADDR+REG_FW_TYPE//0x0B
//REG_EX_FIRMWARE_REVERSION_3		EQU	EDATA 	REG_EX_I2C_ADDR+REG_FIRMWARE_REVERSION_3//0x0C
//REG_EX_FIRMWARE_REVERSION_2		EQU	EDATA 	REG_EX_I2C_ADDR+REG_FIRMWARE_REVERSION_2//0x0D		
//REG_EX_FIRMWARE_REVERSION_1		EQU	EDATA 	REG_EX_I2C_ADDR+REG_FIRMWARE_REVERSION_1//0x0E		
//REG_EX_FIRMWARE_REVERSION_0		EQU	EDATA 	REG_EX_I2C_ADDR+REG_FIRMWARE_REVERSION_0//0x0F		
//REG_EX_FINGERS_GESTURE			EQU	EDATA 	REG_EX_I2C_ADDR+REG_FINGERS_GESTURE//0x10				  
//REG_EX_KEYS_REG					EQU	EDATA 	REG_EX_I2C_ADDR+REG_KEYS_REG//0x11					      
//REG_EX_XY0_COORD_H				EQU	EDATA 	REG_EX_I2C_ADDR+REG_XY0_COORD_H//0x12					   
//REG_EX_X0_COORD_L				EQU	EDATA 	REG_EX_I2C_ADDR+REG_X0_COORD_L					    
//REG_EX_Y0_COORD_L				EQU	EDATA 	REG_EX_I2C_ADDR+REG_Y0_COORD_L				   
//REG_EX_Z0_COORD					EQU	EDATA 	REG_EX_I2C_ADDR+REG_Z0_COORD					     
//REG_EX_XY1_COORD_H				EQU	EDATA 	REG_EX_I2C_ADDR+REG_XY1_COORD_H					   
//REG_EX_X1_COORD_L				EQU	EDATA 	REG_EX_I2C_ADDR+REG_X1_COORD_L					   
//REG_EX_Y1_COORD_L				EQU	EDATA 	REG_EX_I2C_ADDR+REG_Y1_COORD_L					    
//REG_EX_Z1_COORD					EQU	EDATA 	REG_EX_I2C_ADDR+REG_Z1_COORD					      
//REG_EX_XY2_COORD_H				EQU	EDATA 	REG_EX_I2C_ADDR+REG_XY2_COORD_H					    
//REG_EX_X2_COORD_L				EQU	EDATA 	REG_EX_I2C_ADDR+REG_X2_COORD_L					    
//REG_EX_Y2_COORD_L				EQU	EDATA 	REG_EX_I2C_ADDR+REG_Y2_COORD_L					   
//REG_EX_Z2_COORD					EQU	EDATA 	REG_EX_I2C_ADDR+REG_Z2_COORD					      
//REG_EX_XY3_COORD_H				EQU	EDATA 	REG_EX_I2C_ADDR+REG_XY3_COORD_H					   
//REG_EX_X3_COORD_L				EQU	EDATA 	REG_EX_I2C_ADDR+REG_X3_COORD_L					    
//REG_EX_Y3_COORD_L				EQU	EDATA 	REG_EX_I2C_ADDR+REG_Y3_COORD_L				    
//REG_EX_Z3_COORD					EQU	EDATA 	REG_EX_I2C_ADDR+REG_Z3_COORD					      
//REG_EX_XY4_COORD_H				EQU	EDATA 	REG_EX_I2C_ADDR+REG_XY4_COORD_H					    
//REG_EX_X4_COORD_L				EQU	EDATA 	REG_EX_I2C_ADDR+REG_X4_COORD_L				    
//REG_EX_Y4_COORD_L				EQU	EDATA 	REG_EX_I2C_ADDR+REG_Y4_COORD_L					   
//REG_EX_Z4_COORD					EQU	EDATA 	REG_EX_I2C_ADDR+REG_Z4_COORD					      
//REG_EX_XY5_COORD_H				EQU	EDATA 	REG_EX_I2C_ADDR+REG_XY5_COORD_H					   
//REG_EX_X5_COORD_L				EQU	EDATA 	REG_EX_I2C_ADDR+REG_X5_COORD_L					   
//REG_EX_Y5_COORD_L				EQU	EDATA 	REG_EX_I2C_ADDR+REG_Y5_COORD_L					    
//REG_EX_Z5_COORD					EQU	EDATA 	REG_EX_I2C_ADDR+REG_Z5_COORD					      
//
//REG_EX_I2C_DEBUG_0x3E_CMD		EQU	EDATA	REG_EX_I2C_ADDR+0x3E						//0x3E
//REG_EX_CONTACT_COUNT_MAX		EQU	EDATA	REG_EX_I2C_ADDR+REG_CONTACT_COUNT_MAX		//0x3F			  
//
//REG_EX_DATA_OUTPUT_PACKET		EQU	EDATA 	REG_EX_I2C_ADDR+REG_DATA_OUTPUT_PACKET		//0x40
//REG_EX_DATA_OUT_TYPE			EQU	EDATA 	REG_EX_I2C_ADDR+REG_DATA_OUT_TYPE			//REG_DATA_OUTPUT_PACKET
//REG_EX_DATA_OUT_VALID_SIZE		EQU	EDATA 	REG_EX_I2C_ADDR+REG_DATA_OUT_VALID_SIZE		//0x41
//REG_EX_DATA_OUT_START_CH_H		EQU	EDATA 	REG_EX_I2C_ADDR+REG_DATA_OUT_START_CH_H		//0x42
//REG_EX_DATA_OUT_START_CH_L		EQU	EDATA 	REG_EX_I2C_ADDR+REG_DATA_OUT_START_CH_L		//0x43
//REG_EX_DATA_OUT_VALID_RAW		EQU	EDATA 	REG_EX_I2C_ADDR+REG_DATA_OUT_VALID_RAW		//0x44
//
//REG_EX_CMD_IO_CMD_ID			EQU	EDATA	REG_EX_I2C_ADDR+REG_CMD_IO_CMD_ID			//0xD0
//REG_EX_CMD_IO_VALID_SIZE		EQU	EDATA	REG_EX_I2C_ADDR+REG_CMD_IO_VALID_SIZE		//0xD1
//REG_EX_CMD_IO_TYPE				EQU	EDATA	REG_EX_I2C_ADDR+REG_CMD_IO_TYPE				//0xD2
//REG_EX_CMD_IO_SPECIFY_NUMOFBLK	EQU	EDATA	REG_EX_I2C_ADDR+REG_CMD_IO_SPECIFY_NUMOFBLK	//0xD2
//REG_EX_CMD_IO_ADDR_H			EQU	EDATA	REG_EX_I2C_ADDR+REG_CMD_IO_ADDR_H			//0xD3
//REG_EX_CMD_IO_SPECIFY_BLK0		EQU	EDATA	REG_EX_I2C_ADDR+REG_CMD_IO_SPECIFY_BLK0		//0xD3
//REG_EX_CMD_IO_ADDR_L			EQU	EDATA	REG_EX_I2C_ADDR+REG_CMD_IO_ADDR_L			//0xD4
//REG_EX_CMD_IO_SIZE				EQU	EDATA	REG_EX_I2C_ADDR+REG_CMD_IO_SIZE				//0xD5
//REG_EX_CMD_IO_DATA0				EQU	EDATA	REG_EX_I2C_ADDR+REG_CMD_IO_DATA0			//0xD6
//			  
//REG_EX_MISC_INF					EQU	EDATA	REG_EX_I2C_ADDR+REG_MISC_INF				//0xF0
//REG_EX_MISC_CTRL				EQU	EDATA	REG_EX_I2C_ADDR+REG_MISC_CTRL				//0xF1	      
//REG_EX_SMART_WAKEUP_ID			EQU	EDATA	REG_EX_I2C_ADDR+REG_SMART_WAKEUP_ID			//0xF2
//
//REG_EX_CHIP_ID					EQU	EDATA	REG_EX_I2C_ADDR+REG_CHIP_ID					//0xF4	      
//REG_EX_NUM_X					EQU	EDATA	REG_EX_I2C_ADDR+REG_NUM_X					//0xF5	        
//REG_EX_NUM_Y					EQU	EDATA	REG_EX_I2C_ADDR+REG_NUM_Y					//0xF6	       
//REG_EX_NUM_KEY_PROX				EQU	EDATA	REG_EX_I2C_ADDR+REG_NUM_KEY_PROX			//0xF7
//REG_EX_H2D_CMD_PACKET_READY		EQU	EDATA	REG_EX_I2C_ADDR+REG_H2D_CMD_PACKET_READY	//0xF8
//REG_EX_GET_RAW_DATA_PACKET_FINISH	EQU	EDATA	REG_EX_I2C_ADDR+REG_GET_RAW_DATA_PACKET_FINISH//0xF9						      
//
//REG_EX_I2C_DEBUG_0xFA_CMD		EQU	EDATA	REG_EX_I2C_ADDR+0xFA						//0xFA
//REG_EX_I2C_DEBUG_0xFB_CMD		EQU	EDATA	REG_EX_I2C_ADDR+0xFB						//0xFB
//
//REG_EX_MESSAGE_PORT_CMD			EQU	EDATA	REG_EX_I2C_ADDR+REG_MESSAGE_PORT_CMD		//0xFC		
//REG_EX_SUB_PAGE_CMD				EQU	EDATA	REG_EX_I2C_ADDR+REG_SUB_PAGE_CMD			//0xFE
//REG_EX_PAGE_CMD					EQU	EDATA	REG_EX_I2C_ADDR+REG_PAGE_CMD				//0xFF						      


                                                                            

//==[Replace Define]==
#define		REG_REPLACE_PROTOCOL_VER		0x00
#define		REG_REPLACE_PAGE_CMD			0xFF
#define		REG_REPLACE_PAGE_CMD_DEVE_ID	0xEF
//REG_EX_REPLACE_PAGE_CMD			EQU	EDATA	REG_EX_I2C_ADDR+REG_REPLACE_PAGE_CMD


#endif	//__CTI2C_C_FUNCTABLE_DEF_H__